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1 ? fn3123.4 hi-201hs high speed, quad sp st, cmos analog switch the hi-201hs is a monolithic cmos analog switch featuring very fast switching speeds and low on resistance. the integrated circuit consists of four independently selectable spst switches and is pin compatible with the industry standard hi-201 switch. fabricated using silicon-gate technology and the intersil dielectric isolation process, this ttl compatible device offers improved performance over previo usly available cmos analog switches. featuring maximum switching times of 50ns, low on resistance of 50 ? maximum, and a wide analog signal range, the hi-201hs is designed for an y application where improved switching performance, particularly switching speed, is required. (a more detailed discussion on the design and application of the hi-201hs can be found in application note an543.) features ? pb-free available as an option fast switching times -t on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30ns -t off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40ns low ?on? resistance . . . . . . . . . . . . . . . . . . . . . . . . 30 ? pin compatible with standard hi-201 wide analog voltage range ( 15v supplies) . . . . . . . 15v low charge injection ( 15v supplies) . . . . . . . . . . 10pc ttl compatible symmetrical switching analog current range . . . . . 80ma applications high speed multiplexing high frequency analog switching sample and hold circuits digital filters operational amplifier gain switching networks integrator reset circuits pinout (switches shown for logic ?1? input) hi-201hs (cerdip, pdip, soic) top view ordering information part number temp. range (c) package pkg. dwg. # hi1-0201hs-2 -55 to 125 16 ld cerdip f16.3 hi1-0201hs-4 -25 to 85 16 ld cerdip f16.3 hi1-0201hs-5 0 to 75 16 ld cerdip f16.3 hi3-0201hs-5 0 to 75 16 ld pdip e16.3 hi3-0201hs-5z (see note) 0 to 75 16 ld pdip (pb-free) e16.3 hi9p0201hs-5 0 to 75 16 ld soic m16.3 hi9p0201hs-5z (see note) 0 to 75 16 ld soic (pb-free) m16.3 hi9p0201hs-9 -40 to 85 16 ld soic m16.3 hi9p0201hs-9z (see note) -40 to 85 16 ld soic (pb-free) m16.3 note: intersil pb-free products employ special pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which is compatible with both snpb and pb-free soldering operations. intersil pb-free products are msl classified at pb-free peak reflow te mperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020c. 14 15 16 9 13 12 11 10 1 2 3 4 5 7 6 8 a 1 out1 in1 v- gnd in4 a 4 out4 a 2 in2 v+ nc in3 out3 a 3 out2 data sheet september 2004 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 321-724-7143 | intersil (and design) is a registered trademark of intersil americas inc. copyright ? intersil americas inc. 2000, 2004. all rights reserved all other trademarks mentioned are the property of their respective owners. .com .com .com 4 .com u datasheet
2 functional diagram ttl logic input switch cell level shifter and driver gate source drain gate input output v- v+ truth table logic switch 0 1 on off schematic diagrams ttl/cmos reference circuit switch cell p41 v+ mp42 mp43 mp44 qp44 qn44 qn45 c49 c48 v r1 qn43 r42 r41 qn41 qn42 d41 5v d42 5.6v qp42 qp41 v- mn42 mn44 mn45 mp45 mp31 mn32 mp33 mn33 mn31 mp32 analog in analog out q q v- v+ hi-201hs .com .com .com .com 4 .com u datasheet
3 digital input buffer and level shifter schematic diagrams (continued) m n46 m p51 i q i x3 i x4 i x1 q n6 q n7 v r1 i x2 i x3 q p7 q p6 m n52 m n51 i x1 i x2 repeat for each level shifter q n1 c 1 r 1 q p1 i q q n4 q n8 q n9 m p3 m p4 q p9 q p8 m p5 m p7 c ff c 2 q n2 q n5 q p2 r 3 r 2 q p5 q p4 v r1 m p9 m p6 m p10 m n3 m n4 m n5 m n6 m p8 m n7 m n8 m n10 m n9 m p11 m n11 v ee m p12 m n12 q m p13 m n13 v cc m p14 m n14 q m p52 va hi-201hs .com .com .com .com 4 .com u datasheet
4 absolute maximum ratings thermal information supply voltage (v+ to v-). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36v digital input voltage . . . . . . . . . . . . . . . . . . . . . . (v+) +4v to (v-) -4v analog input voltage (one switch) . . . . . . . (v+) +2.0v to (v-) -2.0v peak current, s or d (pulse 1ms, 10% duty cycle max) . . . . 50ma continuous current any terminal (except s or d) . . . . . . . . . 25ma operating conditions temperature ranges hi-201hs-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55 o c to 125 o c hi-201hs-4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -25 o c to 85 o c hi-201hs-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 o c to 75 o c hi-201hs-9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40 o c to 85 o c thermal resistance (typical, note 1) ja ( o c/w) jc ( o c/w) cerdip package. . . . . . . . . . . . . . . . . 80 20 pdip package . . . . . . . . . . . . . . . . . . . 90 n/a soic package . . . . . . . . . . . . . . . . . . . 100 n/a maximum junction temperature ceramic package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 o c plastic package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 o c maximum storage temperature. . . . . . . . . . . . . . . . -65 o c to 150 o c maximum lead temperature (soldering 10s) . . . . . . . . . . . . 300 o c (soic - lead tips only) caution: stresses above those listed in ?a bsolute maximum ratings? may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. note: 1. ja is measured with the component mounted on an evaluation pc board in free air. electrical specifications supplies = +15v, -15v; v ah (logic level high) = 2.4v, v al (logic level low) = +0.8v, gnd = 0v, unless otherwise specified parameter test conditions temp ( o c) -2 -4, -5, -9 units min typ max min typ max dynamic characteristics switch on time, t on (note 3) 25 - 30 50 - 30 50 ns switch off time, t off1 (note 3) 25 - 40 50 - 40 50 ns switch off time, t off2 (note 3) 25 - 150 - - 150 - ns output settling time to 0.1% 25 - 180 - - 180 - ns charge injection, q (note 6) 25 - 10 - - 10 - pc off isolation (note 4) 25 - 72 - - 72 - db crosstalk (note 5) 25 - 86 - - 86 - db input switch capacitance, c s(off) 25 - 10 - - 10 - pf output switch capacitance c d(off) 25 - 10 - - 10 - pf c d(on) 25 - 30 - - 30 - pf digital input capacitance, c a 25 - 18 - - 18 - pf drain-to-source capacitance, c ds(off) 25 - 0.5 - - 0.5 - pf digital input characteristics input low threshold, v al full - - 0.8 - - 0.8 v input high threshold, v ah 25 2.0 - - 2.0 - - v full 2.4 - - 2.4 - - v input leakage current (low), i al 25 - 200 - - 200 - a full - - 500 - - 500 a input leakage current (high), i ah v ah = 4.0v 25 - 20 - - 20 - a full - - 40 - - 40 a analog switch characteristics analog signal range, v s full -15 - +15 -15 - +15 v on resistance, r on (note 2) 25 - 30 50 - 30 50 ? full - - 75 - - 75 ? hi-201hs .com .com .com .com 4 .com u datasheet
5 r on match 25 - 3 - - 3 - % off input leakage current, i s(off) 25 - 0.3 10 - 0.3 10 na full - - 100 - - 50 na off output leakage current, i d(off) 25 - 0.3 10 - 0.3 10 na full - - 100 - - 50 na on leakage current, i d(on) 25 - 0.1 10 - 0.1 10 na full - - 100 - - 50 na power supply characteristics (note 7) power dissipation, p d 25 - 120 - - 120 - mw full - - 240 - - 240 mw current, i+ (pin 13) 25 - 4.5 - - 4.5 - ma full - - 10.0 - - 10.0 ma current, i- (pin 4) 25 - 3.5 - - 3.5 - ma full - - 6 - - 6 ma notes: 2. v out = 10v, i out = 1ma. 3. r l = 1k ? , c l = 35pf, v in = +10v, v a = +3v. (see figure 1). 4. v a = 3v, r l = 1k ? , c l = 10pf, v in = 3v rms , f = 100khz. 5. v a = 3v, r l = 1k ? , v in = 3v rms , f = 100khz. 6. c l = 1nf, v in = 0v, q = c l x ? v o . 7. v a = 3v or v a = 0 for all switches. electrical specifications supplies = +15v, -15v; v ah (logic level high) = 2.4v, v al (logic level low) = +0.8v, gnd = 0v, unless otherwise specified (continued) parameter test conditions temp ( o c) -2 -4, -5, -9 units min typ max min typ max test circuits and waveforms figure 1a. measurement points figure 1b. waveforms digital input switch output v ah = 3.0v 50% v al = 0v 90% 10% t on 50% 0v 90% t off2 t off1 top: logic input (2v/div.) bottom: output (5v/div.) horizontal: 100ns/div. hi-201hs .com .com .com .com 4 .com u datasheet
6 figure 1c. test circuit figure 1. switch t on and t off figure 2a. logic input waveform figure 2b. v in = +10v figure 2c. v in = +5v figure 2d. v in = 0v test circuits and waveforms (continued) v o 3 1 logic input v in = +10v r l 1k ? c l 35pf switch output v+ = +15v 13 v- = -15v 4 switch input gnd v o = v in r l r l + r on 2 5 v a c l includes c fixture + c probe 3 2 1 0 t o logic input (v) +10 +5 0 t o +5 0 t o +5 0 +5 t o hi-201hs .com .com .com .com 4 .com u datasheet
7 application information logic compatibility the hi-201hs is ttl compatible . its logic inputs (pins 1, 8, 9, and 16) are designed to react to digital inputs which exceed a fixed, internally generated ttl switching threshold. the hi-201hs can also be driven with cmos logic (0v-15v), although the switch performance with cmos logic will be inferior to that with ttl logic (0v-5v). the logic input design of the hi-201hs is largely responsible for its fast switching speed. it is a design which features a unique input stage consisting of complementary vertical pnp and npn bipolar transistors. this design differs from that of the standard hi-201 product where the logic inputs are mos transistors. although the new logic design enhances the switching speed performance, it also increases the logic input leakage currents. therefore, the hi-201hs will exhibit larger digital input leakage currents in comparison to the standard hi-201 product. charge injection charge injection is the charge transferred, through the internal gate-to-channel capacitances, from the digital logic input to the analog output. to optimize charge injection performance for the hi-201hs, it is advisable to provide a ttl logic input with fast rise and fall times. if the power supplies are reduced from 15v, charge injection will become increasingly dependent upon the digital input frequency. increased logic input frequency will result in larger output error due to charge injection. power supply considerations the electrical characteristics specified in this data sheet are guaranteed for power supplies v s = 15v. power supply voltages less than 15v will result in reduced switch performance. the following information is intended as a design aid only. single supply the switch operation of the hi-201hs is dependent upon an internally generated switching threshold voltage optimized for 15v power supplies. the hi-201hs does not provide the necessary internal switching threshold in a single supply system. therefore, if single supp ly operation is required, the hi-300 series of switches is recommended. the hi-300 series will remain operational to a minimum +5v single supply. switch performance will degrade as power supply voltage is reduced from optimum levels ( 15v). so it is recommended that a single supply design be thoroughly evaluated to ensure that the switch will meet the requirements of the application. for further information see application notes an520, an521, an531, an532, an543 and an557. figure 2e. v in = -5v figure 2f. v in = -10v figure 2. switching waveforms for various analog input voltages test circuits and waveforms (continued) 0 -5 t o -10 -5 0 t o power supply voltages switch performance 12 v s 15v minimal variation v s < 12v parametric variation becomes increasingly large (increased on resistance, longer switching times). v s < 10v not recommended. v s > 16v not recommended. hi-201hs .com .com .com .com 4 .com u datasheet
8 typical performance curves figure 3. on resistance vs analog signal level figure 4. on resistance vs analog signal level figure 5. i s(off) or i d(off) vs temperature ? figure 6. i d(on) vs temperature ? ? theoretically, leakage current will continue to decrease below 25 o c. but due to environmental conditions, leakage measurements below this temperature are not representative of actual switch performance. figure 7. supply current vs temperature figure 8. leakage current vs analog input voltage -15 -10 -5 0 5 10 15 80 70 60 50 40 30 20 10 0 125 o c v+ = +15v, v- = -15v 25 o c -55 o c analog input (v) on resistance ( ? ) -15 -10 -5 0 5 10 15 80 70 60 50 40 30 20 10 0 v+ = +12v, v- = -12v t a = 25 o c analog input (v) on resistance ( ? ) v+ = +15v, v- = -15v v+ = +8v, v- = -8v v+ = +10v, v- = -10v 25 75 125 temperature ( o c) 0.01 0.10 1.0 10.0 100.0 leakage current (na) 25 75 125 temperature ( o c) 0.01 0.10 1.0 10.0 100.0 leakage current (na) temperature ( o c) 125 105 85 65 45 25 5 -15 -35 -55 7 6 5 4 3 2 1 0 supply current (ma) v+ = +15v, v- = -15v i+ i- 14 12 10 8 6 4 2 0 -2 -4 -6 -8 -10 -12 -14 analog input (v) leakage current (pa) 100 80 60 40 20 0 -20 -40 -60 -80 -100 -120 -140 -160 -180 -200 i don v+ = +15v, v- = -15v i s(off) v d = 0v i d(off) v s = 0v i s(off) /i d(off) hi-201hs .com .com .com .com 4 .com u datasheet
9 figure 9. digital input leakage current vs temperature ? figure 10. leakage current vs analog input voltage ? theoretically, leakage current will continue to decrease below 25 o c. but due to environmental conditions, leakage measurements below this temperature are not representative of actual switch performance. figure 11. switching time vs temperature figure 12. switching time vs supply voltage figure 13. switching time vs positive supply voltage figure 14. switching time vs negative supply voltage typical performance curves (continued) temperature ( o c) 125 115 105 95 85 75 65 55 45 25 v al = 0v, v ah2 = 3v, v ah1 = 5v 35 60 40 20 0 -20 -40 -60 -80 -100 -120 -140 -160 -180 -200 -220 -240 -260 -280 leakage current ( a) i ah1 i ah2 i al 16.0 15.5 15.0 14.5 -14.0 -14.5 -15.0 -15.5 -16.0 14.0 analog input (v) 10 9 8 7 6 5 4 3 2 1 0 -1 -2 -3 -4 -5 -6 -7 -8 -9 -10 v+ = +15v, v- = -15v, t a = 25 o c i s(off) v d = 0v i d(off) v s = 0v leakage current (na) temperature ( o c) 125 105 85 65 45 25 5 -15 -35 -55 180 160 140 120 100 80 60 40 20 0 switching time (ns) t off2 t off1 t on v+ = +15v v- = -15v r l = 1k ? c l = 35pf supply voltage ( v) r l = 1k ? , c l = 35pf, t a = 25 o c t off2 t off1 t on 56789101112131415 350 300 250 200 150 100 50 0 switching time (ns) positive supply (v) v- = -15v, r l = 1k ? t off2 t off1 t on 56789101112131415 350 300 250 200 150 100 50 switching time (ns) c l = 35pf, t a = 25 o c 0 negative supply (v) t off2 t off1 t on -5 -6 -7 -8 -9 -10 -11 -12 -13 -14 -15 350 300 250 200 150 100 50 0 switching time (ns) v+ = +15v, r l = 1k ? c l = 35pf, t a = 25 o c hi-201hs .com .com .com .com 4 .com u datasheet
10 figure 15. switching time vs input logic voltage figure 16. input switching threshold vs supply voltage figure 17. charge injection vs analog voltage figure 18. capacitance vs analog voltage figure 19. off isolation vs frequency figure 20. crosstalk vs frequency typical performance curves (continued) digital input voltage (v) t off2 t off1 t on 012345 350 300 250 200 150 100 50 0 switching time (ns) v + = +15v, v- = -15v, r l = 1k ? c l = 35pf, v al = 0v, t a = 25 o c supply voltage ( v) 10 11 12 13 14 15 9 8 7 6 5 0 3.0 2.5 2.0 1.8 1.5 1.0 0.5 input logic threshold (v) analog input (v) -10 -5 0 5 10 -10 -20 -30 -40 -50 50 40 30 20 10 0 v+ = +15v, v- = -15v c l = 1nf q v a c l in out ? v o q = c l x ? v o charge injection (pc) analog input (v) -15 -5 0 5 15 40 c d(on) 10 -10 c d(off) or c s(off) c ds(off) 35 30 25 20 15 10 5 0 capacitance (pf) v+ = +15v, v- = -15v v in = 3v rms , v a = 3v r l = 100 ? r l = 1k ? r l in out v in v o off isolation = 20 log v in v o frequency (hz) 10m 1m 100k 10k 140 120 100 80 60 40 20 0 off isolation (db) frequency (hz) 10m 1m 100k 10k 140 120 100 80 60 40 20 0 crosstalk (db) v+ = +15v, v- = -15v v in = 3v rms , v a = 3v r l = 1k ? in out v in v o1 crosstalk = 20 log v o2 v o1 v o2 r l = 1k ? hi-201hs .com .com .com .com 4 .com u datasheet
11 all intersil semiconductor products are manufactured, assembled and tested under iso9000 quality systems certification. intersil semiconductor products are sold by description only. intersil corporation reserves the right to make changes in circui t design and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reli- able. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of patents o r other rights of third parties which may result from its use. no license is granted by implication or otherwise unde r any patent or patent rights of intersil or its subsidiaries. for information regarding intersil corporation and its products, see web site www.intersil.com die characteristics die dimensions 2440 m x 2860 m x 485 m metallization ty p e : c u a l thickness: 16k ? 2k ? passivation type: nitride over silox nitride thickness: 3.5k ? 1k ? silox thickness: 12k ? 2k ? worst case current density 9.5 x 10 4 a/cm 2 metallization mask layout hi-201hs a1 a2 out2 in2 v+ in3 out3 a3 a4 out4 in4 gnd v- in1 out1 hi-201hs .com .com .com 4 .com u datasheet

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